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1 lt3437 3437fc high voltage power conversion 14v and 42v automotive systems industrial power systems distributed power systems battery-powered systems powered ethernet high voltage 500ma, 200khz step-down switching regulator with 100 a quiescent current wide input range: 3.3v to 60v load dump (input transient) protection to 80v 500ma peak switch current burst mode operation: 100 a quiescent current** low shutdown current: i q < 1 a defeatable burst mode operation 200khz switching frequency saturating switch design: 0.8 ? on-resistance peak switch current maintained over full duty cycle range* 1.25v feedback reference voltage easily synchronizable soft-start capability small 10-pin thermally enhanced dfn package the lt ? 3437 is a 200khz monolithic buck switching regulator that accepts input voltages up to 80v. a high efficiency 500ma, 0.8 ? switch is included on the die along with all the necessary oscillator, control and logic cir- cuitry. current mode topology is used for fast transient response and good loop stability. innovative design techniques along with a new high volt- age process achieve high efficiency over a wide input range. efficiency is maintained over a wide output current range by employing burst mode operation at low currents, utilizing the output to bias the internal circuitry, and by using a supply boost capacitor to fully saturate the power switch. burst mode operation can be defeated by a logic high signal on the sync pin which results in lower light load ripple at the expense of light load efficiency. patented circuitry maintains peak switch current over the full duty cycle range.* shutdown reduces input supply current to less than 1 a. external synchronization can be imple- mented by driving the sync pin with logic-level inputs. a single capacitor from the c ss pin to the output provides a controlled output voltage ramp (soft-start). the lt3437 is available in a low profile (0.75mm) 3mm 3mm 10-pin dfn package or a 16-pin tssop package, both with exposed pad leadframes for low thermal resistance. features descriptio u applicatio s u typical applicatio u , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. *protected by u.s. patents, including 6498466. **see burst mode operation section for conditions. v in shdn boost v bias lt3437 2.2 f 100v cer 330pf 0.1 f 0.1 f 100 h bas21 sync gnd 100 f 6.3v tant v out 3.3v 400ma v in 4.5v to 80v* 10mq100n 1500pf 25k 165k 100k 3437 ta01 27pf sw c ss v c fb *for input voltages above 60v restrictions apply 14v to 3.3v step-down converter with 100 a no load quiescent current supply current vs input voltage input voltage (v) 0 0 supply current ( a) 40 100 10 20 30 40 3437 ta02 50 200 20 60 80 120 140 160 180 80 60 70 input voltage transient response load dump cold crank v in 20v/div v out 20mv/div ac coupled v in 0v 3437 ta03 50ms/div i out 250ma
2 lt3437 3437fc the denotes the specifications which apply over the ?0 c to 125 c temperature range, otherwise specifications are at t j = 25 c. v in = 12v, shdn = 12v, bias = 5v, fb = 1.25v, c ss /sync = 0v unless otherwise noted. LT3437EFE lt3437ife lt3437hfe order part number lt3437edd lt3437idd consult ltc marketing for parts specified with wider operating temperature ranges. dd part marking order part number fe part marking order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ v in , shdn, bias, sw operating ............................. 60v v in , shdn 100ms transient, <15% duty cycle ....... 80v boost pin above sw ............................................ 35v boost pin voltage operating ................................. 75v boost pin 100ms transient, <15% duty cycle ...... 85v sync, c ss , fb .......................................................... 6v ja = 45 c/w, jc(pad) = 10 c/w exposed pad is gnd (pin 11) must be soldered to gnd (pin 4) operating junction temperature range lt3437edd (note 2) ....................... C 40 c to 125 c lt3437idd (note 2) ........................ C 40 c to 125 c LT3437EFE (note 2) ........................ C 40 c to 125 c lt3437ife (note 2) ......................... C 40 c to 125 c lt3437hfe (note 2) .......................... C40 c to 140 c storage temperature range ................. C 65 c to 125 c dd package ....................................... C65 c to 125 c fe package ........................................ C65 c to 150 c fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 nc sw nc v in nc boost nc gnd nc shdn sync nc fb v c bias c ss 17 ja = 45 c/w, jc(pad) = 10 c/w exposed pad is gnd (pin 17) must be soldered to gnd (pin 8) 3437efe 3437ife 3437hfe lbdj lbdk (note 1) symbol parameter conditions min typ max units v shdn shdn threshold 1.15 1.3 1.45 v i shdn shdn input current shdn = 12v 530 a minimum input voltage (note 3) 2.5 3 v i vins supply shutdown current shdn = 0v, boost = 0v, fb/pgfb = 0v, bias = 0v 0.1 2 a supply sleep current (note 4) bias = 0v, fb = 1.35v 150 300 a fb = 1.35v 45 75 a absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics top view dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 shdn sync fb v c bias sw v in boost gnd c ss 11
3 lt3437 3437fc symbol parameter conditions min typ max units i vin supply quiescent current bias = 0v, fb = 1.15v, v c = 0.8v, sync = 2v 1.35 2 ma bias = 5v, fb = 1.15v, v c = 0.8v, sync = 2v 0.475 1 ma minimum bias voltage (note 5) 2.7 3.15 v i biass bias sleep current (note 4) 110 180 a i bias bias quiescent current sync = 2v 0.75 1 ma minimum boost voltage (note 6) i sw = 500ma 1.8 2.5 v input boost current (note 7) i sw = 0.5a 11 16 ma i sw = 0.25a 8 13 ma v ref reference voltage (v ref ) 3.3v < v vin < 80v 1.225 1.25 1.275 v i fb fb input bias current 50 200 na ea voltage gain (note 8) 900 v/v ea voltage g m di(v c )= 10 a 650 mho ea source current fb = 1.15v 15 35 55 a ea sink current fb = 1.35v 15 30 55 a v c to sw g m 1a/v v c switching threshold v sync = 2v 500 mv v c high clamp 1.5 1.75 2.1 v i pk sw current limit 500 650 900 ma sw v cesat switch saturation voltage i sw = 250ma 200 400 mv (note 9) i sw = 500ma 400 800 mv switching frequency 165 200 240 khz maximum duty cycle 95 % minimum sync amplitude 1.5 2 v sync frequency range 240 700 khz sync input impedance 50 k ? i css c ss current threshold (note 10) fb = 0v 4 10 16 a the denotes the specifications which apply over the ?0 c to 125 c temperature range, otherwise specifications are at t j = 25 c. v in = 12v, shdn = 12v, bias = 5v, fb = 1.25v, c ss /sync = 0v unless otherwise noted. electrical characteristics the denotes the specifications which apply over the ?0 c to 140 c temperature range, otherwise specifications are at t j = 25 c. v in = 12v, shdn = 12v, bias = 5v, fb = 1.25v, c ss /sync = 0v unless otherwise noted. symbol parameter conditions min typ max units v shdn shdn threshold 1.1 1.3 1.5 v i shdn shdn input current shdn = 12v 530 a minimum input voltage (note 3) 2.5 3.5 v i vins supply shutdown current shdn = 0v, boost = 0v, fb/pgfb = 0v, bias = 0v 0.1 2 a supply sleep current (note 4) bias = 0v, fb = 1.35v 150 300 a fb = 1.35v 45 75 a electrical characteristics
4 lt3437 3437fc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3437edd/LT3437EFE are guaranteed to meet performance specifications from 0 c to 125 c junction temperature. specifications over the C40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3437idd/lt3437ife are guaranteed and tested over the full C40 c to 125 c operating junction temperature range. the lt3437hfe is also tested to the lt3437 electrical characteristics table at 140 c operating junction temperature. high junction temperatures degrade operating lifetimes. note 3: minimum input voltage is defined as the voltage where switching starts. actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. see applications information. note 4: supply input current is the quiescent current drawn by the input pin. its typical value depends on the voltage on the bias pin and operating state of the lt3437. with the bias pin at 0v, all of the quiescent current required to operate the lt3437 will be provided by the v in pin. with the bias voltage above its minimum input voltage, a portion of the total quiescent current will be supplied by the bias pin. supply sleep current is defined as the quiescent current during the sleep portion of burst mode operation. see applications information for determining application supply currents. note 5: minimum bias voltage is the voltage on the bias pin when i bias is sourced into the pin. note 6: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. note 7: boost current is the current flowing into the boost pin with the pin held 3.3v above input voltage. it flows only during switch on time. note 8: gain is measured with a v c swing from 1.15v to 750mv. note 9: switch saturation voltage guaranteed by correlation to wafer level measurements for dd package parts. note 10: the c ss threshold is defined as the value of current sourced into the c ss pin which results in an increase in sink current from the v c pin. see the soft-start section in applications information. i vin supply quiescent current bias = 0v, fb = 1.15v, v c = 0.8v, sync = 2v 1.35 2 ma bias = 5v, fb = 1.15v, v c = 0.8v, sync = 2v 0.475 1 ma minimum bias voltage (note 5) 2.7 3.15 v i biass bias sleep current (note 4) 110 180 a i bias bias quiescent current sync = 2v 0.75 1 ma minimum boost voltage (note 6) i sw = 500ma 1.8 2.5 v input boost current (note 7) i sw = 0.5a 11 16 ma i sw = 0.25a 8 13 ma v ref reference voltage (v ref ) 3.3v < v vin < 60v 1.212 1.25 1.288 v v vin = 80v 1.190 1.25 1.288 v i fb fb input bias current 50 200 na ea voltage gain (note 8) 900 v/v ea voltage g m di(v c )= 10 a 650 mho ea source current fb = 1.15v 15 35 55 a ea sink current fb = 1.35v 15 30 55 a v c to sw g m 1a/v v c switching threshold v sync = 2v 500 mv v c high clamp 1.5 1.75 2.1 v i pk sw current limit 400 650 900 ma sw v cesat switch saturation voltage i sw = 250ma 200 400 mv (note 9) i sw = 500ma 400 800 mv switching frequency 140 200 240 khz maximum duty cycle 95 % minimum sync amplitude 1.5 2 v sync frequency range 240 500 khz sync input impedance 50 k ? i css c ss current threshold (note 10) fb = 0v 4 10 16 a the denotes the specifications which apply over the ?0 c to 140 c temperature range, otherwise specifications are at t j = 25 c. v in = 12v, shdn = 12v, bias = 5v, fb = 1.25v, c ss /sync = 0v unless otherwise noted. electrical characteristics
5 lt3437 3437fc temperature ( c) C50 i vin ( a) 800 700 600 500 400 300 200 100 0 110 3437 g08 C10 30 70 150 90 C30 10 50 130 run mode sleep mode temperature ( c) 0 i vin ( a) 200 400 600 100 300 500 C10 30 70 110 3437 g07 150 C30 C50 10 50 90 130 run mode sleep mode v bias = 0v sleep mode v bias = 5v efficiency and power loss vs load current load current (ma) 0.1 0 efficiency (%) 20 10 40 50 60 100 100 3437 g01 30 1 10 1000 70 80 90 500 450 400 350 300 250 200 150 100 50 0 power loss (mw) efficiency power loss v in = 12v v out = 3.3v t a = 25 c 1.20 fb voltage (v) 1.24 1.30 1.22 1.28 1.26 temperature ( c) 3437 g02 C50 0 50 75 C25 25 100 150 125 temperature ( c) 150 frequency (khz) 160 180 190 200 220 3437 g03 170 230 240 250 210 C50 0 50 75 C25 25 100 150 125 voltage (v) 1.35 3437 g04 1.20 1.10 1.40 1.45 1.50 1.30 1.25 1.15 temperature ( c) C50 0 50 75 C25 25 100 150 125 v shdn (v) 0 0 i shdn ( a) 2 4 6 10 20 30 40 3437 g05 50 8 10 60 current ( a) 3437 g06 6 4 2 0 10 8 16 14 12 22 18 temperature ( c) 20 C50 0 50 75 C25 25 100 150 125 v vin = 80v v vin = 12v v vin = 60v temperature ( c) 0 peak switch current (ma) 200 100 300 400 500 600 700 800 3437 g09 C50 0 50 75 C25 25 100 150 125 typical perfor a ce characteristics uw fb voltage vs temperature oscillator frequency vs temperature shdn threshold shutdown supply current vs temperature input current vs temperature bias current vs temperature switch peak current limit vs temperature shdn pin current
6 lt3437 3437fc on-time (ns) 3437 g16 0 500 450 400 350 300 250 200 150 100 50 temperature ( c) C50 0 50 75 C25 25 100 150 125 load current (ma) 100 6 boost current (ma) 8 12 11 200 400 3437 g17 7 10 9 300 500 input voltage (v) 2.0 0 3.0 output voltage (v) 0.5 1.5 2.0 2.5 4.0 4.0 3437 g18 1.0 3.0 2.5 3.5 4.5 3.5 v out = 3.3v i load = 250ma boost diode = diodes inc b1100 supply current vs input voltage burst mode threshold vs input voltage oscillator frequency vs fb voltage switch on voltage (v cesat ) load current (ma) 0 voltage (mv) 200 600 500 200 400 500 3437 g12 100 400 300 100 300 t j = 125 c t j = C40 c t j = 25 c typical perfor a ce characteristics uw minimum input voltage fb voltage (v) 0 0 frequency (khz) 50 100 150 0.25 0.50 0.75 3437 g11 1.00 200 250 1.25 input voltage (v) 0 0 supply current ( a) 40 100 10 20 30 40 3437 f13 50 200 20 60 80 120 140 160 180 80 60 70 v out = 3.3v load current (ma) 0 3.0 input voltage (v) 3.5 4.5 5.0 5.5 400 7.5 3437 g14 4.0 200 100 300 500 6.0 6.5 7.0 5v to run 5v to start 3.3v to run 3.3v to start input voltage (v) 0 0 load current (ma) 200 20 40 50 3437 g15 100 80 60 40 20 120 140 160 180 10 30 60 enter exit v out = 3.3v minimum on-time boost current vs load current dropout operation fb voltage (v) 0 0 i css ( a) 10 20 30 0.2 0.4 0.6 0.8 3437 g10 1.0 35 5 15 25 1.2 soft-start defeated soft-start current threshold vs fb voltage
7 lt3437 3437fc typical perfor a ce characteristics uw burst mode operation burst mode defeated v out 20mv/div ac coupled i sw 100ma/div v in = 12v 10 s/div 3437 g23 v out = 3.3v i q = 100 a v out 20mv/div ac coupled i sw 100ma/div 10 s/div 3437 g24 step response step response v out 50mv/div i out 100ma/div 1ms/div 3437 g25 load step 0ma to 200ma v out 50mv/div i out 100ma/div 1ms/div 3437 g26 load step 100ma to 300ma maximum duty cycle vs temperature maximum duty cycle (%) 3437 g20 94.0 91.5 94.5 93.0 93.5 92.0 92.5 temperature ( c) i load = 250ma C50 0 50 75 C25 25 100 150 125 v c switching threshold vs temperature maximum sync frequency vs temperature v c voltage (v) 3437 g21 0.5 0 0.6 0.3 0.4 0.1 0.2 temperature ( c) C50 0 50 75 C25 25 100 150 125 C50 0 50 75 C25 25 100 150 125 maximum sync frequency (khz) 3437 g22 600 400 1600 900 1000 1200 1400 1100 1300 1500 700 800 500 temperature ( c) v in = 12v v out = 3.3v i out = 100ma dropout operation input voltage (v) 2.0 0 4 output voltage (v) 1 2 3 4.0 6 3437 g19 3.0 2.5 3.5 5.0 4.5 6.0 5.5 5 v out = 5v i load = 250ma boost diode = diodes inc b1100 v in = 12v v out = 3.3v i q = 1.7ma v sync = 3.3v
8 lt3437 3437fc and its voltage loss approximates that of a 0.8 ? fet structure. gnd (pins 4, 11/ pins 8, 17): the gnd pin connection acts as the reference for the regulated output, so load regulation will suffer if the ground end of the load is not at the same voltage as the gnd pin of the ic. this condition will occur when load current or other currents flow through metal paths between the gnd pin and the load ground. keep the path between the gnd pin and the load ground short and use a ground plane when possible. the gnd pin also acts as a heat sink and should be soldered (along with the exposed leadframe) to the cop- per ground plane to reduce thermal resistance (see appli- cations information). c ss (pin 5/pin 9): a capacitor from the c ss pin to the regulated output voltage determines the output voltage ramp rate during start-up. when the current through the c ss capacitor exceeds the c ss threshold (i css ), the volt- age ramp of the output is limited. the c ss threshold is proportional to the fb voltage (see typical performance characteristics) and is defeated for fb voltage greater than 0.9v (typical). see soft-start section in applications infor- mation for details. uu u pi fu ctio s sw (pin 1/pin 2): the sw pin is the emitter of the on-chip power npn switch. this pin is driven up to the input pin voltage during switch on time. inductor current drives the sw pin negative during switch off time. negative voltage is clamped with an external schottky catch diode to pre- vent excessive negative voltages. nc (pins 1, 3, 5, 7, 13, 16)(fe package only): no connection. the nc pins are electrically isolated from the lt3437. the nc pins may be connected to pcb traces to aid pcb layout. v in (pin 2/pin 4): this is the collector of the on-chip power npn switch. v in powers the internal control circuitry when a voltage on the bias pin is not present. high di/dt edges occur on this pin during switch turn on and off. keep the path short from the v in pin through the input bypass capacitor, through the catch diode back to sw. all trace inductance on this path will create a voltage spike at switch off, adding to the v ce voltage across the internal npn. boost (pin 3/pin 6): the boost pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar npn power switch. without this added voltage, the typical switch voltage loss would be about 1.5v. the additional boost voltage allows the switch to saturate (dd/fe)
9 lt3437 3437fc uu u pi fu ctio s (dd/fe) bias (pin 6/pin 10): the bias pin is used to improve efficiency when operating at higher input voltages and light load current. connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its operating current from the output voltage rather than the input supply. this architecture increases efficiency especially when the input voltage is much higher than the output. minimum output voltage setting for this mode of operation is typically 2.7v. v c (pin 7/pin 11): the v c pin is the output of the error amplifier and the input of the peak switch current comparator. it is normally used for frequency compensation, but can also serve as a current clamp or control loop override. v c sits at about 0.45v for light loads and 1.5v at maximum load. during the sleep portion of burst mode operation, the v c pin is held at a voltage slightly below the burst threshold for better transient response. driving the v c pin to ground will disable switching and place the ic into sleep mode. fb (pin 8/pin 12): the feedback pin is used to determine the output voltage using an external voltage divider from the output that generates 1.25v at the fb pin. when the fb pin drops below 0.9v, switching frequency is reduced, the sync function is disabled and output ramp rate control is enabled via the c ss pin. see the feedback section in applications information for details. sync (pin 9/pin 14): the sync pin is used to synchronize the internal oscillator to an external signal. it is directly logic compatible and can be driven with any signal be- tween 25% and 75% duty cycle. the synchronizing range is equal to maximum initial operating frequency up to 700khz. when the voltage on the fb pin is below 0.9v the sync function is disabled. when a synchronization signal or logic-level high is present at the sync pin, burst mode operation is disabled. see the synchronizing section in applications information for details. shdn (pin 10/pin 15): the shdn pin is used to turn off the regulator and to reduce input current to less than 1 a. the shdn pin requires a voltage above 1.3v with a typical source current of 5 a to take the ic out of the shutdown state. exposed pad (pin 11/pin 17): ground. must be soldered to the pcb.
10 lt3437 3437fc the lt3437 is a constant frequency, current mode buck converter. this means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. in addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. a switch cycle starts with an oscilla- tor pulse which sets the rs latch to turn the switch on. when switch current reaches a level set by the current compara- tor, the latch is reset and the switch turns off. output volt- age control is obtained by using the output of the error amplifier to set the switch current trip point. this technique means that the error amplifier commands current to be delivered to the output rather than voltage. a voltage fed system will have low phase shift up to the resonant fre- quency of the inductor and output capacitor, then an abrupt 180 shift will occur. the current fed system will have 90 phase shift at a much lower frequency, but will not have the additional 90 shift until well beyond the lc resonant fre- quency. this makes it much easier to frequency compen- sate the feedback loop and gives much quicker transient response and line rejection. most of the circuitry of the lt3437 operates from an internal 2.4v bias line. the bias regulator normally draws power from the v in pin, but if the bias pin is connected to an external voltage higher than 2.7v, bias power will be drawn from the external source (typically the regulated output voltage). this improves efficiency. high switch efficiency is attained by using the boost pin to provide a voltage to the switch driver which is higher than the input voltage, allowing the switch to be saturated. this boosted voltage is generated with an external capaci- tor and diode. to further optimize efficiency, the lt3437 automatically switches to burst mode operation in light load situations. in burst mode operation, all circuitry associated with control- ling the output switch is shut down, reducing the input supply current to 45 a and bias input current to 110 a. if lower output ripple is desired over light load efficiency, burst mode operation can be defeated by setting the sync pin voltage greater than 2v. a logic-level low on the shdn pin disables the ic and reduces input supply current to less than 1 a. external synchronization can be implemented by driving the sync pin with logic-level inputs. block diagra w figure 1. lt3437 block diagram fb v c internal ref undervoltage lockout thermal shutdown soft-start foldback detect slope comp antislope comp 2.4v C + 1.3v 1.25v shdn c ss sync bias v in shdn comp C + C + error amp burst mode detect 200khz oscillator switch latch current comp driver circuitry r q sw s boost pgnd gnd v c clamp 3437 bd
11 lt3437 3437fc applicatio s i for atio wu uu feedback pin functions the feedback (fb) pin on the lt3437 is used to set output voltage and provide several overload protection features. the first part of this section deals with selecting resistors to set output voltage, and the remaining part talks about frequency foldback and soft-start features. please read both parts before committing to a final design. referring to figure 2, the output voltage is determined by a voltage divider from v out to ground which generates 1.25v at the fb pin. since the output divider is a load on the output, care must be taken when choosing the resistor divider values. for light load applications the resistor values should be as large as possible to achieve peak efficiency in burst mode operation. extremely large values for resistor r1 will cause an output voltage error due to the 50na fb pin input current. the suggested value for the output divider resistor (see figure 2) from fb to ground (r2) is 100k or less. a formula for r1 is shown below. a table of standard 1% values is shown in table 1 for common output voltages. rr v rna out 12 125 125 2 50 = + ? C. .? figure 2. feedback network more than just voltage feedback the fb pin is used for more than just output voltage sensing. it also reduces switching frequency and con- trols the soft-start voltage ramp rate when output voltage is below the regulated level (see the frequency foldback and soft-start current graphs in typical performance characteristics). frequency foldback is done to control power dissipation in both the ic and in the external diode and inductor during short-circuit conditions. a shorted output requires the switching regulator to operate at very low duty cycles. as a result, the average current through the diode and induc- tor is equal to the short-circuit current limit of the switch (typically 500ma for the lt3437). minimum switch on time limitations would prevent the switcher from attaining a sufficiently low duty cycle if switching frequency were maintained at 200khz, so frequency is reduced by about 10:1 when the fb pin voltage drops below 0.4v (see frequency foldback graph). as the feedback voltage rises, the switching frequency increases to 200khz with 0.95v on the fb pin. during frequency foldback, external syn- chronization is disabled to prevent interference with fold- back operation. frequency foldback does not affect opera- tion during normal load conditions. in addition to lowering switching frequency, the soft-start ramp rate is also affected by the feedback voltage. large capacitive loads or high input voltages can cause a table 1 output r1 output voltage r2 nearest (1%) error (v) (k ? , 1%) (k ? )(%) 2.5 100 100 0 3 100 140 0 3.3 100 165 0.38 5 100 300 0 6 100 383 0.63 8 100 536 C 0.63 10 100 698 C 0.25 12 100 866 0.63 soft-start foldback detect 200khz oscillator + C error amp 1.25v v c 7 fb 8 c ss v out 5 sw lt3437 c1 r1 r2 3437 f02 1
12 lt3437 3437fc surge of current in the input leads that will store energy in the parasitic inductance of the leads. this energy will cause the input voltage to swing above the dc level of input power source and it may exceed the maximum voltage rating of the input capacitor and lt3437. all input voltage transient sequences should be observed at the v in pin of the lt3437 to ensure that absolute maximum voltage ratings are not violated. the easiest way to suppress input voltage transients is to add a small aluminum electrolytic capacitor in parallel with the low esr input capacitor. the selected capacitor needs to have the right amount of esr to critically damp the resonant circuit formed by the input lead inductance and the input capacitor. the typical values of esr will fall in the range of 0.5 ? to 2 ? and capacitance will fall in the range of 5 f to 50 f. if tantalum capacitors are used, values in the 22 f to 470 f range are generally needed to minimize esr and meet ripple current and surge ratings. care should be taken to ensure the ripple and surge ratings are not exceeded. the avx tps and kemet t495 series are surge rated. avx recommends derating capacitor operating voltage by 2:1 for high surge applications. output capacitor the output capacitor is normally chosen by its effective series resistance (esr) because this is what deter- mines output ripple voltage. to get low esr takes volume, so physically smaller capacitors have higher esr. the esr range for typical lt3437 applications is 0.05 ? to 0.2 ? . a typical output capacitor is an avx type tps, 100 f at 10v, with a guaranteed esr less than 0.1 ? . this is a d size surface mount solid tantalum capacitor. tps capacitors are specially con- structed and tested for low esr, so they give the lowest esr for a given volume. the value in microfarads is not particularly critical, and values from 22 f to greater than 500 f work well, but you cannot cheat mother nature on esr. if you find a tiny 22 f solid tantalum capacitor, it will have high esr and output ripple high input current surge during start-up. the soft-start function reduces input current surge by regulating switch current via the v c pin to maintain a constant voltage ramp rate (dv/dt) at the output. a capacitor (c1 in figure 2) from the c ss pin to the output determines the maximum output dv/dt. when the feedback voltage is below 0.4v, the v c pin will rise, resulting in an increase in switch current and output voltage. if the dv/dt of the output causes the current through the c ss capacitor to exceed i css , the v c voltage is reduced resulting in a constant dv/dt at the output. as the feedback voltage increases, i css increases, resulting in an increased dv/dt until the soft-start function is defeated with 0.9v present at the fb pin. the soft-start function does not affect operation during normal load conditions. however, if a momentary short (brown out condition) is present at the output which causes the fb voltage to drop below 0.9v, the soft-start circuitry will become active. input capacitor step-down regulators draw current from the input supply in pulses. the rise and fall times of these pulses are very fast. the input capacitor is required to reduce the voltage ripple this causes at the input of lt3437 and force the switching current into a tight local loop, thereby minimizing emi. the rms ripple current can be calculated from: i i v vvv ripple rms out in out in out () C = () ceramic capacitors are ideal for input bypassing. at 200khz switching frequency input capacitor values in the range of 2.2 f to 10 f are suitable for most applications. if opera- tion is required close to the minimum input required by the lt3437, a larger value may be required. this is to prevent excessive ripple causing dips below the minimum operat- ing voltage resulting in erratic operation. input voltage transients caused by input voltage steps, or by hot plugging the lt3437 to a pre-powered source such as a wall adapter, can exceed maximum v in ratings. the sudden application of input voltage will cause a large applicatio s i for atio wu u u
13 lt3437 3437fc is high enough at the switching frequency, output ripple voltage (although smaller for a ceramic output capacitor) may still affect the proper operation of the regulator. a filter capacitor c f in parallel with the r c /c c network, along with a small feedforward capacitor c fb , is suggested to control possible ripple at the v c pin. the lt3437 can be stabilized using a 100 f ceramic output capacitor and v c component values of c c = 1500pf, r c = 25k, c f = 330pf and c fb =27pf. output ripple voltage figure 3 shows a typical output ripple voltage waveform for the lt3437. ripple voltage is determined by the impedance of the output capacitor and ripple current through the inductor. peak-to-peak ripple current through the inductor into the output capacitor is: i vvv vlf out in out in p-p = () ()()() C for high frequency switchers the ripple current slew rate is also relevant and can be calculated from: di dt v l in = peak-to-peak output ripple voltage is the sum of a triwave created by peak-to-peak ripple current times esr and a square wave created by parasitic inductance (esl) and ripple current slew rate. capacitive reactance is assumed to be small compared to esr or esl. v i esr esl di dt ripple = ()( ) + () p-p example: with v in = 12v, v out = 3.3v, l = 100 h, esr = 0.075 ? , esl = 10nh: i p-p = ()( ) () ? ()() = == 33 12 33 12 100 6 200 3 0 120 12 100 6 012 6 .C. . C . ee a di dt e e v ripple = (0.120a)(0.075) + (10e C 9)(0.12e6) = 0.009 + 0.0012 = 10.2mv p-p voltage could be unacceptable. table 2 shows some typical solid tantalum surface mount capacitors. table 2. surface mount solid tantalum capacitor esr and ripple current e case size esr max ( ? ) ripple current (a) avx tps 0.1 to 0.3 0.7 to 1.1 d case size avx tps 0.1 to 0.3 0.7 to 1.1 c case size avx tps 0.2 0.5 many engineers have heard that solid tantalum capacitors are prone to failure if they undergo high surge currents. this is historically true, and type tps capacitors are specially tested for surge capability, but surge ruggedness is not a critical issue with the output capacitor. solid tantalum capacitors fail during very high turn-on surges which do not occur at the output of regulators. high discharge surges, such as when the regulator output is dead shorted, do not harm the capacitors. unlike the input capacitor rms, ripple current in the output capacitor is normally low enough that ripple cur- rent rating is not an issue. the current waveform is triangular with a typical value of 30ma rms . the formula to calculate this is: output capacitor ripple current (rms) i vvv lfv ripple rms out in out in () .C = ()( ) ()()( ) = 029 12 i p-p ceramic capacitors higher value, lower cost ceramic capacitors are now becoming available. they are generally chosen for their good high frequency operation, small size and very low esr (effective series resistance). low esr reduces output ripple voltage but also removes a useful zero in the loop frequency response, common to tantalum capacitors. to compensate for this, a resistor r c can be placed in series with the v c compensation capacitor c c (figure 10). care must be taken, however, since this resistor sets the high frequency gain of the error amplifier, including the gain at the switching frequency. if the gain of the error amplifier applicatio s i for atio wu u u
14 lt3437 3437fc discontinuous operation occurs when: i vvv lfv out dis out in out in () C ()()( ) () 2 for v out = 5v, v in = 8v and l = 68 h: i ee a out max () .C C C .C. . = ()( ) ()()() == 05 58 5 2 68 6 200 3 8 0 5 0 069 0 431 note that there is less load current available at the higher input voltage because inductor ripple current increases. at v in = 15v, duty cycle is 33% and for the same set of conditions: i ee a out max () .C C C .C. . = ()( ) ()()() == 05 515 5 2 68 6 200 3 15 0 5 0 121 0 379 to calculate actual peak switch current in continuous mode with a given set of conditions, use: ii vvv lfv sw pk out out in out in () C =+ () ()()( ) 2 if a small inductor is chosen which results in discontinuous mode operation over the entire load range, the maximum load current is equal to: i iflv vvv out max pk in out in out () C = ()( )( ) ()( ) 2 2 2 maximum output load current maximum load current for a buck converter is limited by the maximum switch current rating (i pk ). the current rating for the lt3437 is 500ma. unlike most current mode converters, the lt3437 maximum switch current limit does not fall off at high duty cycles. most current mode converters suffer a drop off of peak switch current for duty cycles above 50%. this is due to the effects of slope compensation required to prevent subharmonic oscilla- tions in current mode converters. (for detailed analysis, see application note 19.) the lt3437 is able to maintain peak switch current limit over the full duty cycle range by using patented circuitry to cancel the effects of slope compensation on peak switch current without affecting the frequency compensation it provides. maximum load current would be equal to maximum switch current for an infinitely large inductor, but with finite inductor size, maximum load current is reduced by one-half peak-to-peak inductor current. the following formula assumes continuous mode operation, implying that the term on the right (i p-p /2) is less than i out . ii vvv lfv i i out max pk out in out in pk p () C C C = ()( ) ()()( ) = 2 -p 2 figure 3. lt3437 ripple voltage waveform v out 10mv/div 100 f tantalum esr 75m ? v out 10mv/div 100 f ceramic v sw 10v/div v in = 12v 1 s/div 3437 f03 v out = 3.3v i load = 500ma l = 100 h applicatio s i for atio wu u u
15 lt3437 3437fc choosing the inductor for most applications the output inductor will fall in the range of 68 h to 220 h. lower values are chosen to reduce physical size of the inductor. higher values allow more output current because they reduce peak current seen by the lt3437 switch, which has a 0.5a limit. higher values also reduce output ripple voltage and reduce core loss. when choosing an inductor you might have to consider maximum load current, core and copper losses, allow- able component height, output voltage ripple, emi, fault current in the inductor, saturation and of course cost. the following procedure is suggested as a way of han- dling these somewhat complicated and conflicting requirements. 1. choose a value in microhenries such that the maximum load current plus half of the inductor ripple current is less than the minimum peak switch current (i pk ). choosing a small inductor with lighter loads may result in discontinuous mode of operation, but the lt3437 is designed to work well in either mode. assume that the average inductor current is equal to load current and decide whether or not the inductor must withstand continuous fault conditions. if maxi- mum load current is 0.25a, for instance, a 0.25a inductor may not survive a continuous minimum peak switch current overload condition. for applications with a duty cycle above 50%, the inductor value should be chosen to obtain an inductor ripple current of less than 40% of the peak switch current. 2. calculate peak inductor current at full load current to ensure that the inductor will not saturate. peak current can be significantly higher than output current, especially with smaller inductors and lighter loads, so do not omit this step. powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. other core materials fall somewhere in between. the following formula assumes continuous mode of opera- tion, but it errs only slightly on the high side for discon- tinuous mode, so it can be used for all conditions. ii vvv flv peak out out in out in =+ () ()( )( ) C 2 v in = maximum input voltage f = switching frequency, 200khz 3. decide if the design can tolerate an open core geom- etry like a rod or barrel, which has high magnetic field radiation, or whether it needs a closed core like a toroid, to prevent emi problems. this is a tough decision because the rods or barrels are temptingly cheap and small, and there are no helpful guidelines to calculate when the magnetic field radiation will be a problem. 4. after making an initial choice, consider the secondary things like output voltage ripple, second sourcing, etc. use the experts in linear technologys applications department if you feel uncertain about the final choice. they have experience with a wide range of inductor types and can tell you about the latest developments in low profile, surface mounting, etc. table 3. inductor selection criteria vendor/ value i dc(max) dcr height part no. ( h) (ma) (ohms) (mm) coiltronics up1b-101 100 530 1.11 5.0 up1b-151 150 460 1.61 5.0 up2b-221 220 380 1.96 5.0 coilcraft d01605t-473mx 47 450 1.1 1.8 d01605t-104mx 100 300 2.3 1.8 d03308p-154 150 600 0.94 3.0 d03308p-224 220 500 1.6 3.0 sumida cdrh4d28-470 47 480 0.387 3.0 cdrh4d28-101 100 290 1.02 3.0 cdrh5d28-101 100 420 0.520 3.0 applicatio s i for atio wu u u
16 lt3437 3437fc v out 1v/div v in = 12v 1ms/div 3437 f04 c out = 100 f i load = 200ma c ss = gnd c ss = 0.1 f c ss = 0.01 f figure 4. v out dv/dt short-circuit considerations the lt3437 is a current mode controller. it uses the v c node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. the internal clamp on the v c node, nominally 1.5v, then acts as an output switch peak current limit. this action becomes the switch current limit specification. the maximum available output power is then determined by the switch current limit. a potential controllability problem could occur under short-circuit conditions. if the power supply output is short circuited, the feedback amplifier responds to the low output voltage by raising the control voltage, v c , to its peak current limit value. ideally, the output switch would be turned on, and then turned off as its current exceeded the value indicated by v c . however, there is finite response time involved in both the current comparator and turn-off of the output switch. this results in a minimum on time t on(min). when combined with the large ratio of v in to (v f + i ? r), the diode forward voltage plus inductor i ? r voltage drop, the potential exists for a loss of control. expressed mathematically the requirement to maintain control is: ft vir v on f in ? ? + where: f = switching frequency t on = switch on time v f = diode forward voltage v in = input voltage i ? r = inductor i ? r voltage drop if this condition is not observed, the current will not be limited at i pk but will cycle-by-cycle ratchet up to some higher value. using the nominal lt3437 clock frequency of 200khz, a v in of 40v and a (v f + i ? r) of say 0.7v, the maximum t on to maintain control would be approximately 90ns, an unacceptably short time. the solution to this dilemma is to slow down the oscillator to allow the current in the inductor to drop to a sufficiently low value such that the current does not continue to ratchet higher. when the fb pin voltage is abnormally low, thereby indicating some sort of short-circuit condition, the oscillator frequency will be reduced. oscillator fre- quency is reduced by a factor of 10 when the fb pin voltage is below 0.4v and increases linearly to its typical value of 200khz at a fb voltage of 0.95v (see typical performance characteristics). these oscillator frequency reductions during short-circuit conditions allow the lt3437 to main- tain current control soft-start for applications where [v in /(v out + v f )] >10 or large input surge currents cannot be tolerated, the lt3437 soft-start feature should be used to control the output capacitor charge rate during start-up, or during recovery from an output short circuit, thereby adding additional control over peak inductor current. the soft-start function limits the switch current via the v c pin to maintain a constant voltage ramp rate (dv/dt) at the output capacitor. a capaci- tor (c1 in figure 2) from the c ss pin to the regulated output voltage determines the output voltage ramp rate. when the current through the c ss capacitor exceeds the c ss threshold (i css ), the voltage ramp of the output capacitor is limited by reducing the v c pin voltage. the c ss threshold is proportional to the fb voltage (see typical performance characteristics) and is defeated for fb voltages greater than 0.9v (typical). the output dv/dt can be approxi- mated by: dv dt i c css ss = but actual values will vary due to start-up load conditions, compensation values and output capacitor selection. applicatio s i for atio wu u u
17 lt3437 3437fc burst mode operation to enhance efficiency at light loads, the lt3437 automati- cally switches to burst mode operation which keeps the output capacitor charged to the proper voltage while minimizing the input quiescent current. during burst mode operation, the lt3437 delivers short bursts of current to the output capacitor followed by sleep periods where the output power is delivered to the load by the output capacitor. in addition, v in and bias quiescent currents are reduced to typically 45 a and 110 a, respec- tively, during the sleep time. as the load current decreases towards a no load condition, the percentage of time that the lt3437 operates in sleep mode increases and the average input current is greatly reduced, resulting in higher efficiency. the minimum average input current depends on the v in to v out ratio, v c frequency compensation, feedback divider network and schottky diode leakage. it can be approxi- mated by the following equation: iii v v iii in avg vins shdn out in biass fb s () ? ++ ? ? ? ? ? ? ++ () () where i vins = input pin current in sleep mode v out = output voltage v in = input voltage i biass = bias pin current in sleep mode i fb = feedback network current i s = catch diode reverse leakage at v out = low current efficiency (non burst mode operation) example: for v out = 3.3v, v in = 12v iaa aa in avg () . . ? ++ ? ? ? ? ? ? + + 45 5 33 12 110 12 5 0 .. . 5 08 45 5 42 92 () () =++= a aa a a during the sleep portion of the burst mode cycle, the v c pin voltage is held just below the level needed for normal operation to improve transient response. see the typical performance characteristics section for burst and tran- sient response waveforms. if burst mode operation is undesirable, it can be defeated by placing 2v or greater on the sync pin. when burst mode operation is defeated, output ripple at light loads will be reduced at the expense of light load efficiency. catch diode the catch diode carries load current during the sw off time. the average diode current is therefore dependent on the switch duty cycle. at high input to output voltage ratios, the diode conducts most of the time. as the ratio approaches unity, the diode conducts only a small fraction of the time. the most stressful condition for the diode is when the output is short circuited. under this condition, the diode must safely handle i peak at maximum duty cycle. to maximize high and low load current efficiency, a fast switching diode with low forward drop and low reverse leakage should be used. low reverse leakage is critical to maximize low current efficiency since its value over tem- perature can potentially exceed the magnitude of the lt3437 supply current. low forward drop is critical for high current efficiency since the loss is proportional to forward drop. figure 5. i q vs v in input voltage (v) 0 0 supply current ( a) 40 100 10 20 30 40 3435 f05 50 200 20 60 80 120 140 160 180 80 60 70 v out = 3.3v applicatio s i for atio wu u u
18 lt3437 3437fc these requirements result in the use of a schottky type diode. dc switching losses are minimized due to its low forward voltage drop, and ac behavior is benign due to its lack of a significant reverse recovery time. schottky diodes are generally available with reverse voltage ratings of 60v, and even 100v, and are price competitive with other types. the use of so-called ultrafast recovery diodes is gener- ally not recommended. when operating in continuous mode, the reverse recovery time exhibited by ultrafast diodes will result in a slingshot type effect. the power internal switch will ramp up v in current into the diode in an attempt to get it to recover. when the diode has finally turned off, some tens of nanoseconds later, the v sw node voltage ramps up at an extremely high dv/dt, perhaps 5v to even 10v/ns! with real world lead inductances, the v sw node can easily overshoot the v in rail. this can result in poor rfi behavior, and if the overshoot is severe enough, damage the ic itself. boost pin for most applications, the boost components are a 0.1 f capacitor and a bas21 diode. the anode is typically connected to the regulated output voltage, to generate a voltage approximately v out above v in to drive the output stage (figure 6a). however, the output stage discharges the boost capacitor during the on time of the switch. the output driver requires at least 2.5v of headroom through- out this period to keep the switch fully saturated. if the output voltage is less than 3.3v, it is recommended that an alternate boost supply is used. the boost diode can be connected to the input (figure 6b), but care must be taken to prevent the boost voltage (v boost = v in ? 2) from exceeding the boost pin absolute maximum rating. the additional voltage across the switch driver also increases power loss and reduces efficiency. if available, an inde- pendent supply can be used to generate the required boost voltage (figure 6c). tying boost to v in or an independent supply may reduce efficiency, but it will reduce the minimum v in required to start-up with light loads. if the generated boost voltage dissipates too much power at maximum load, the boost voltage the lt3437 sees can be reduced by placing a zener diode in series with the boost diode (figure 6a option). a 0.1 f boost capacitor is recommended for most appli- cations. almost any type of film or ceramic capacitor is suitable, but the esr should be <1 ? to ensure it can be fully recharged during the off time of the switch. the capacitor value is derived from worst-case conditions of 4700ns on time, 11ma boost current and 0.7v discharge ripple. the boost capacitor value could be reduced under less demanding conditions, but this will not improve circuit operation or efficiency. under low input voltage and low load conditions, a higher value capacitor will reduce discharge ripple and improve start-up operation. boost lt3437 v boost C v sw = v out v boost(max) = v in + v out v in v out optional (6a) v in sw gnd boost lt3437 v boost C v sw = v dc v boost(max) = v dc + v in v in v dc d ss 3437 f06 v out (6c) v in sw gnd boost lt3437 v boost C v sw = v in v boost(max) = 2v in v in v out (6b) v in sw gnd figure 6. boost pin configurations applicatio s i for atio wu u u
19 lt3437 3437fc shutdown function and undervoltage lockout the shdn pin on the lt3437 controls the operation of the ic. when the voltage on the shdn pin is below the 1.3v shutdown threshold, the lt3437 is placed in a zero supply current state. driving the shdn pin above the shutdown threshold enables normal operation. the shdn pin has an internal sink current with a typical value of 5 a. in addition to the shutdown feature, the lt3437 has an undervoltage lockout function. when the input voltage is below 2.5v, switching will be disabled. the undervoltage lockout threshold doesnt have any hysteresis and is mainly used to insure that all internal voltages are at the correct level before switching is enabled. if an undervolt- age lockout function with hysteresis is needed to limit input current at low v in to v out ratios, refer to figure 7 and the following: vr v r v r iv v vr r uvlo shdn shdn shdn shdn hyst out =++ ? ? ? ? ? ? + = () 1 32 1 3 r1 should be chosen to minimize quiescent current during normal operation by the following equation: r vv i in shdn typ 1 2 15 = () () C . () example: r a m r m m a m k 1 12 2 155 13 3 513 1 65 1 13 649 408 = () = ? = ? () = ?? ? ? = C . . . . CC . . (nearest 1% 6.49m ) r2 = 1.3 7 C 1.3 1.3m (nearest 1% 412k) see the typical performance characteristics section for graphs of shdn and v in currents verses input voltage. figure 7. undervoltage lockout synchronizing oscillator synchronization to an external input is achieved by connecting a ttl logic-compatible square wave with a duty cycle between 25% and 75% to the lt3437 sync pin. the synchronizing range is equal to initial operating frequency up to 700khz . this means that minimum practical sync frequency is equal to the worst-case high self-oscillating frequency ( 240khz ), not the typical oper- ating frequency of 200khz . caution should be used when synchronizing above 300khz, because at higher sync frequencies the amplitude of the internal slope compen- sation used to prevent subharmonic switching is re- duced. this type of subharmonic switching only occurs at input voltages less than twice output voltage. higher inductor values will tend to eliminate this problem. see frequency compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensa- tion. application note 19 has more details on the theory of slope compensation. if the fb pin voltage is below 0.9v (power-up or output short-circuit conditions), the sync function is disabled. this allows the frequency foldback to operate to avoid hazardous conditions for the sw pin. if a synchronization signal or logic-level above 2v is present at the sync pin, burst mode operation is disabled. burst mode operation can be enabled or disabled on the fly. if no synchronization or burst mode defeat is required, this pin should be connected to ground. applicatio s i for atio wu u u enable 1.3v 3437 f07 5 a shdn r2 2.5v C + shdn comp C + v in comp 10 v in v out lt3437 2 r1 r3
20 lt3437 3437fc layout considerations as with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. for maximum efficiency, switch rise and fall times are typically in the nanosecond range. to prevent noise both radiated and conducted, the high speed switching current path, shown in figure 8, must be kept as short as possible. this is implemented in the suggested layouts of figure 9. shortening this path will also reduce the parasitic trace inductance of approximately 25nh/inch. at switch off, this parasitic inductance produces a flyback spike across the lt3437 switch. when operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the lt3437 that may exceed its absolute maximum rating. a ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. the v c and fb components should be kept as far away as possible from the switch and boost nodes. the lt3437 pinout has been designed to aid in this. the ground for these components should be separated from the switch current path. failure to do so will result in poor stability or subharmonic oscillation. board layout also has a significant effect on thermal resistance. pin 4/pin 8 and the exposed die pad, pin 11/pin 17, are connected by a continuous copper plate that runs under the lt3437 die. this is the best thermal path for heat out of the package. reducing the thermal resistance from pin 4 and the exposed pad onto the board will reduce die temperature and increase the power capability of the lt3437. this is achieved by providing as much copper area as possible around the exposed pad. adding multiple solder filled feedthroughs, under and around this pad, to an internal ground plane will also help. similar treatment to the catch diode and coil terminations will reduce any additional heating effects. figure 8. high speed switching path c2 c1 3437 f08 d1 l1 v in lt3437 v out v in sw high frequency circulation path + load applicatio s i for atio wu u u
21 lt3437 3437fc figure 9. suggested layouts 3437 f09b c1 c2 d1 l1 fe package topside metal dd package topside metal applicatio s i for atio wu u u
22 lt3437 3437fc applicatio s i for atio wu u u thermal calculations power dissipation in the lt3437 chip comes from four sources: switch dc loss, switch ac loss, boost circuit current, and input quiescent current. the following formu- las show how to calculate each of these losses. these formulas assume continuous mode operation, and should not be used for calculating efficiency at light load currents. switch loss: p ri v v tivf sw sw out out in eff out in = ()( ) + ()( )()() 2 12 / boost current loss: p vi v boost out out in = () () 2 30 / quiescent current loss: p q = v in (500 a) + v out (800 a) r sw = switch resistance ( 1 when hot ) t eff = effective switch current/voltage overlap time (t r + t f + t ir + t if ) t r = (v in /0.6)ns t f = (v in /2)ns t ir = t if = (i out /0.05)ns f = switch frequency example: with v in = 40v, v out = 5v and i out = 250ma: pe w pw pw sw boost q = ()( )() + () () ()()( ) += = () () = = () + () = 1 0 25 5 40 92 12 0 25 40 200 3 0 008 0 092 0 1 502530 40 0 005 40 0 0005 5 0 0008 0 024 2 2 . /. ... ./ . ... total power dissipation is: p tot = 0.1 + 0.065 + 0.024 = 0.13w thermal resistance for the lt3437 package is influenced by the presence of internal or backside planes. with a full plane under the package, thermal resistance will be about 45 c for the fe and dd packages. no plane will increase resistance to about 150 c/w. to calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature: t j = t a + q ja (p tot ) with the dd package (q ja = 45 c/w) at an ambient temperature of 70 c: t j = 70 + 45(0.1) = 74.5 c high temperature operation extreme care must be taken when designing lt3437 applications to operate at high ambient temperatures. the lt3437 is designed to work at elevated temperatures but erratic operation can occur due to external components. each passive component should be checked for absolute value and voltage ratings to ensure loop stability at tem- perature. boost and catch diode leakages, as well as increased series resistance, will adversely affect efficiency and low quiescent current operation. junction tempera- ture increase in the diodes due to self heating (leakage) and power dissipation should be measured to ensure their maximum temperature specifications are not violated. input voltage vs operating frequency considerations the absolute maximum input supply voltage for the lt3437 is specified at 80v. this is based solely on internal semi- conductor junction breakdown effects. due to internal power dissipation, the actual maximum v in achievable in a particular application may be less than this. a detailed theoretical basis for estimating internal power loss is given in the section thermal considerations. note that ac switching loss is proportional to both operating frequency and output current. the majority of ac switch- ing loss is also proportional to the square of input voltage. for example, while the combination of v in = 40v, v out = 5v at 700ma and f osc = 200khz may be easily achievable, simultaneously raising v in to 80v and f osc to 700khz is not possible. nevertheless, input voltage transients up to 80v can usually be accommodated, assuming the resulting
23 lt3437 3437fc increase in internal dissipation is of insufficient time dura- tion to raise die temperature significantly. a second consideration is controllability. a potential limi- tation occurs with a high step-down ratio of v in to v out , as this requires a correspondingly narrow minimum switch on time. an approximate expression for this (assuming continuous mode operation) is given as follows: t on(min) = (v out + v f )/v in (f osc ) where: v in = input voltage v out = output voltage v f = schottky diode forward drop f osc = switching frequency a potential controllability problem arises if the lt3437 is called upon to produce an on time shorter than it is able to produce. feedback loop action will lower, then reduce, the v c control voltage to the point where some sort of cycle- skipping or burst mode behavior is exhibited. in summary: 1. be aware that the simultaneous requirements of high v in , high i out and high f osc may not be achievable in practice due to internal dissipation. the thermal con- siderations section offers a basis to estimate internal power. in questionable cases, a prototype supply should be built and exercised to verify acceptable operation. 2. the simultaneous requirements of high v in , low v out and high f osc can result in an unacceptably short mini- mum switch on time. cycle skipping and/or burst mode behavior will result causing an increase in output volt- age ripple while maintaining the correct output voltage. frequency compensation before starting on the theoretical analysis of frequency response, the following should be rememberedthe worse the board layout, the more difficult the circuit will be to stabilize. this is true of almost all high frequency analog circuits. read the layout considerations section first. common layout errors that appear as stability problems are distant placement of input decoupling capacitor and/or catch diode, and connecting the v c compensation to a ground track carrying significant switch current. in addi- tion, the theoretical analysis considers only first order non-ideal component behavior. for these reasons, it is important that a final stability check is made with produc- tion layout and components. the lt3437 uses current mode control. this alleviates many of the phase shift problems associated with the inductor. the basic regulator loop is shown in figure 10. the lt3437 can be considered as two g m blocks, the error amplifier and the power stage. figure 11 shows the overall loop response. at the v c pin, the frequency compensation components used are: r c = 25k, c c = 1500pf and c f = 330pf. the output capacitor used is a 100 f, 10v tantalum capacitor with typical esr of 100m ? . the esr of the tantalum output capacitor provides a useful zero in the loop frequency response for maintaining stabil- ity. this esr, however, contributes significantly to the ripple voltage at the output (see output ripple voltage in the applications information section). it is possible to reduce capacitor size and output ripple voltage by replac- ing the tantalum output capacitor with a ceramic output capacitor because of its very low esr. the zero provided by the tantalum output capacitor must now be reinserted back into the loop. alternatively, there may be cases where, even with the tantalum output capacitor, an addi- tional zero is required in the loop to increase phase margin for improved transient response. applicatio s i for atio wu u u
24 lt3437 3437fc applicatio s i for atio wu u u figure 10. model for loop response C + current mode power stage g m = 1 ? g m = 650 ? 1.25v v c lt3437 error amp 1.6m r c r1 fb sw esr output r2 c out 3437 f13 c fb c f c c figure 11. overall loop response frequency (hz) C180 C160 C140 C120 C100 C80 C60 C40 C20 phase (deg) 0 C40 gain (db) 0 60 40 20 C20 80 100 100 1k 10k 100k 3437 f12 1m 10 v out = 3.3v c out = 100 f, 0.1 ? c f = 330pf r c = 25k c c = 1500pf i load = 250ma a zero can be added into the loop by placing a resistor (r c ) at the v c pin in series with the compensation capacitor, c c , or by placing a capacitor (c fb ) between the output and the fb pin. when using r c , the maximum value has two limitations. first, the combination of output capacitor esr and r c may stop the loop rolling off altogether. second, if the loop gain is not rolled off sufficiently at the switching frequency, output ripple will perturb the v c pin enough to cause unstable duty cycle switching, similar to subharmonic oscillations. if needed, an additional capacitor (c f ) can be added across the r c /c c network from the v c pin to ground to further suppress v c ripple voltage. with a tantalum output capacitor, the lt3437 already includes a resistor (r c ) and filter capacitor (c f ) at the v c pin (see figures 10 and 11) to compensate the loop over the entire v in range (to allow for stable pulse skipping for high v in -to-v out ratios 10). a ceramic output capacitor can still be used with a simple adjustment to the resistor r c for stable operation (see ceramic capacitors section for stabilizing lt3430). if additional phase margin is required, a capacitor (c fb ) can be inserted between the output and fb pin, but care must be taken for high output voltage applications. sudden shorts to the output can create unacceptably large negative transients on the fb pin. for v in -to-v out ratios < 10, higher loop bandwidths are possible by readjusting the frequency compensation com- ponents at the v c pin. when checking loop stability, the circuit should be oper- ated over the applications full voltage, current and tem- perature range. proper loop compensation may be obtained by empirical methods, as described in application notes 19 and 76.
25 lt3437 3437fc u package descriptio dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) 3.00 0.10 (4 sides) 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd10) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc
26 lt3437 3437fc fe16 (bc) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.94 (.116) 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation bc u package descriptio
27 lt3437 3437fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 14v to 3.3v step-down converter with 100 a no load quiescent current supply current vs input voltage input voltage (v) 0 0 supply current ( a) 40 100 10 20 30 40 3435 ta05 50 200 20 60 80 120 140 160 180 80 60 70 typical applicatio u load current (ma) 0.1 0 efficiency (%) 20 10 40 50 60 100 100 3437 g01 30 1 10 1000 70 80 90 500 450 400 350 300 250 200 150 100 50 0 power loss (mw) efficiency power loss v in = 12v v out = 3.3v t a = 25 c efficiency and power loss vs load current v in shdn boost lt3437 2.2 f 100v cer 330pf 0.1 f 0.1 f 100 h bas21 sync gnd 100 f 6.3v tant v out 3.3v 400ma v in 4.5v to 80v* 10mq100n 1500pf 25k 165k 100k 3437 ta04 27pf sw c ss v c fb *for input voltages above 60v, some restrictions may apply v bias
28 lt3437 3437fc ? linear technology corporation 2005 lt 0107 rev c ? printed in usa related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com part number description comments lt1765 25v, 3a (i out ), 1.25mhz, high efficiency step-down dc/dc v in : 3v to 25v, v out(min) = 1.20v, i q = 1ma, i sd < 15 a, converter so-8, tssop16e lt1766 60v, 1.2a (i out ), 200khz, high efficiency step-down dc/dc v in : 5.5v to 60v, v out(min) = 1.20v, i q = 2.5ma, converter i sd < 25 a, tssop16/e lt1767 25v, 1.5a (i out ), 1.25mhz, high efficiency step-down dc/dc v in : 3v to 25v, v out(min) = 1.20v, i q = 1ma, i sd < 6 a, converter ms8/e lt1776 40v, 550ma (i out ), 200khz, high efficiency step-down dc/dc v in : 7.4v to 40v, v out(min) = 1.24v, i q = 3.2ma, converter i sd < 30 a, n8, s8 lt1936 36v, 1.4a, 500khz, high efficiency step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 1.2v, i q = 1.8ma, i sd 4ma ms8/e lt1940 dual 1.2a (i out ), 1.1mhz, high efficiency step-down dc/dc v in : 3v to 25v, v out(min) = 1.2v, i q = 3.8ma, tssop-16e converter lt1956 60v, 1.2a (i out ), 500khz, high efficiency step-down dc/dc v in : 5.5v to 60v, v out(min) = 1.20v, i q = 2.5ma, converter i sd < 25 a, tssop16/e lt1976 60v, 1.5a (i out ), 200khz, high efficiency step-down dc/dc v in : 3.3v to 60v, i q = 100 a, i sd < 1 a, tssop-16e converter lt1977 60v, 1.5a (i out ), 500khz, high efficiency step-down dc/dc v in : 3.3v to 60v, i q = 100 a, i sd < 1 a, tssop-16e converter lt3010 80v, 50ma, low noise linear regulator v in : 1.5v to 80v, v out(min) = 1.28v, i q = 30 a, i sd < 1 a, ms8e lt3430 60v, 2.5a (i out ), 200khz, high efficiency step-down dc/dc v in : 5.5v to 60v, v out(min) = 1.20v, i q = 2.5ma, converter i sd < 30 a, tssop-16e lt3431 60v, 2.5a (i out ), 500khz, high efficiency step-down dc/dc v in : 5.5v to 60v, v out(min) = 1.20v, i q = 2.5ma, converter i sd < 30 a, tssop-16e lt3433 60v, 400ma (i out ), 200khz/500khz, buck-boost dc/dc converter v in : 5v to 60v, v out : 3.3v to 20v, i q = 100 a, tssop-16e lt3434/lt3435 60v, 3a (i out ), 200khz, high efficiency step-down dc/dc converter v in : 3.3v to 60v, i q = 100 a, i sd < 1 a, tssop-16e lt3470 40v, 300ma, micropower buck regulator with integrated boost and v in : 4v to 40v, v out(min) = 1.25v, i q = 26 a, thinsot catch diodes ltc3727/ltc3727-1 36v, 500khz, high efficiency step-down dc/dc controllers v in : 4v to 36v, v out(min) = 0.8v, i q = 670 a, i sd < 20 a, qfn-32, ssop-28

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